[Verilog] Arithmetic Shift

Hey everyone, I am working on a project for a Logic Circuits course that consists of many parts. The focus of this project is to build a minimized CPU at the end of the semester.

The first part of the project is building an 8-bit ALU (Arithmetic Logic Unit) using Xilix ISE. We have been given the option to do it as schematics or as Verilog (similar to VHDL) and i have chosen to do it in Verilog. I was able to construct all the operations (And, Or, Add, Subtract, SLTU, SRL, SLL) except SRA (Shift right arithmetic) and SLA (shift left arithmetic) . Lots of verilog references use both <<< and >>> operators to apply an arithmetic shift but this did not seem to work with me.

Below is the code of what i have done so far:

module ALU8( input [7:0] A,B,
input [2:0] S,shift,
input cin, binv,
output reg [7:0] y,
output Cout,ovr,zero
    );
	 wire [7:0] Sint, Bint ;
	 wire slt0;
	 wire sltu0;
	
	 wire C7;
	 
	 always @ (*)
	 begin
	 case (S) 
	 3'b000: y= A&B;
	 3'b001: y= A|B;
	 3'b010: y=A^B;
	 3'b011: y=Sint;
	 3'b100: y={{7'b0},slt0};
	 3'b101: y={{7'b0},sltu0};
	 3'b110: y=A << shift;
    3'b111: y={A[0],A[1],A[2],A[3],A[4],A[5],A[6],A[7]} << shift; 
	 			
	
    default: y= 8'b0;
	 endcase
	 end
	 assign ovr=C7^Cout;
	 assign Bint=binv? ~B:B;
	 assign slt0= Sint[7]^ovr;
	 assign sltu0= Sint[7]^(~Cout);// since if cout=0 then ovr=1
	 assign {C7,Sint[6:0]}= A[6:0]+Bint[6:0]+cin;
	 assign {Cout, Sint [7]}= A[7]+Bint[7]+ C7;
	 assign zero=~|y;


endmodule

Also, we get extra grades for an efficient design so i was trying to use one shifter unit to do all the shift operations.

So my question is that why the arithmetic shift operators are not working? Or is there another way to do this shift?

P.S: I am not looking for anyone to do my project or anything but I am looking forward for just some tips that can help me solve this issue and Thanks.